Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to solve DLL false locking

Status
Not open for further replies.

raymond_luo2003

Member level 1
Joined
May 20, 2004
Messages
41
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
464
Dear friend,

Usually the purpose of DLL is providing the multiphase clocks with same frequency as the input clock. And the phase shift of the whole delay line is 2-phi. But if the delay range of DLL delay stage is large, the DLL can lock to 4-phi or 2n-phi (n>2) of delay. This false locking will cause the intermediate phases of the delay line to vary from the desired value.

I am confused how to make a circuit to avoid the above problem. Any reference paper and real circuit are well appreciated!


Thanks and best regards,
Raymond
 


Dear Friend,
May I know how many taps I mean how many delay stages your DLL has got? Because depending upon the number of delay stages we can build up a decoding circuit that will avoid false locking.
 

let your dll start working from phase less than 2Pi ( in other words, the minum deley). Then it will lock at 2pi.
 

Thanks all your reply!

My architecture have 4 phases clocks.
As for the setting the delay of this DLL less than 2phi at initial stage, I agree with that. But how about the DLL got big noise at half way of operation, then the DLL lost the lock, then the DLL got chance to false locked to a 4Phi ???
Am I right?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top