lahrach
Full Member level 3
Hello friends,
I want replicate a design 500 times in order to occupy all the FPGA area, how can I do it with VHDL ?
the port map of 500 designs is a tedious operation!
best regards
I want replicate a design 500 times in order to occupy all the FPGA area, how can I do it with VHDL ?
the port map of 500 designs is a tedious operation!
best regards