How to reduce the MOS OFF capacitance?

[iVenky]

Hi,

I am trying to design a capacitor bank for VCO. The thing is the MOSFET switches give a considerable OFF cap when they are OFF because of which I am seeing a reducing the capacitor range in the bank. I would like to reduce this OFF capacitance of the MOSFET and I don't want to reduce the size further because this would increase the ON switch resistance. Is there any technique to reduce this capacitance?

Please let me know if you have any questions.

Thanks!

 

[dick_freebird]

Some options if you are willing and allowed to touch details
of device design (not accept the PCells as-offered). How
much of the capacitance is in interconnect, how well you
share S/D (multistripe) and so on. Be sure you care more
about Ron than Coff, which you may not (esp. at the lower
C bits - use wider at higher C, smaller proportionally at lower
C where it impacts net Q least).

 

[dick_freebird]

Also, consider topology. For example if the C bank is
shunt-to-ground, put the switches on the ground side
and the net Coff becomes the series value, with several
of the FET capacitances returning to ground instead of
a more sensitive circuit node.

 

[Nig]

This is a classical problem in VCO design. I will try to summarize the options assuming you have a NMOS switches in the cap bank.

1 - Check whether the NMOS switch can be turned ON with a higher voltage. This decreases the RON and to achieve a given ON switch resistance you can get a smaller device and hence smaller parasitic

2 - This is a tricky one in layout. Can you add a high resistance to common path ( like vss) so that the parasitic caps have a very very low Q and hence wont act as a cap in high frequencies? This will not effect your performance.

If you are generally getting a CON/COFF ratio to be around 3 then you are good enough and you may not be able to improve more than that. Else you have to sacrifice Q of the cap bank.