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How to recover the clock without using PLL?

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YOu need two delay circuits. One to produce double edge clock using XOR (any period <<<50% of T is ok since only leading edge is used to reduce jitter) show below.


The Decoder latch uses a 2nd time delay that is leading edge trigger and non-retrigerable for the duration of 3/4 T where T is the symbol time to latch input data to decode correct phase of clock. Then this second clock is used to decode state of input to recover the data.
Screen shot 2012-07-28 at 1.56.30 PM.png
YOu can choose any Manchester protocol. Biø-M, Biø-S or Biø-I for mark, space or invert.
 
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    iVenky

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YOu need two delay circuits. One to produce double edge clock using XOR (any period <<<50% of T is ok since only leading edge is used to reduce jitter) show below.


The Decoder latch uses a 2nd time delay that is leading edge trigger and non-retrigerable for the duration of 3/4 T where T is the symbol time to latch input data to decode correct phase of clock. Then this second clock is used to decode state of input to recover the data.
View attachment 77850
YOu can choose any Manchester protocol. Biø-M, Biø-S or Biø-I for mark, space or invert.

I see that you have included the first delay circuit. I would be really happy if you could tell me about the second delay circuit. How to have a circuit that is leading edge triggerable and non-triggerable for 3/4 T?

Thanks a lot.
 

YOu need two delay circuits. One to produce double edge clock using XOR (any period <<<50% of T is ok since only leading edge is used to reduce jitter) show below.


The Decoder latch uses a 2nd time delay that is leading edge trigger and non-retrigerable for the duration of 3/4 T where T is the symbol time to latch input data to decode correct phase of clock. Then this second clock is used to decode state of input to recover the data.
View attachment 77850
YOu can choose any Manchester protocol. Biø-M, Biø-S or Biø-I for mark, space or invert.

Hello sir. I am waiting for your reply.

Thanks a lot.
 

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