How to provide SATA interface for OMAP35XX processor?

[manu.s]

I want to provide a SATA interface for OMAP35xx processor from TI.The OMAP35xx doesn't have a built-in SATA or ATA controller.The different possibilities analysed were
1.To provide an external SATA controller using higher end FPGA and treat it as a memory mapped I/O -is a costly solution

2.To provide an external ATA controller (in CPLD) and use an external PATA to SATA bridge IC.
(AS per my understanding,a throughput greater than 16.7 MB/s for ATA is only possible with Ultra DMA mode of operation.Not know much about Ultra DMA, but the OMAp35xx doesn't have an ultra DMA mode of operation)

3.To provide a USB to SATA converter bridge IC .(here the theoretical maximum throughput possible is 480Mb/s of HI speed USB)

Please comment on these.Also suggest the best solutions possible for SATA interface with OMAP35xx?

manu

 

[farhada]

It all depends on what is your end goal of this project it.
Are you planning to make a product that will go into production or is it just for a hubby design?

Using an FPGA as a SATA controller is both expensive and DIFFICULT, I would not even think about that as a solution.

It is pretty easy to implement a PATA interface on OMAP35xx, you can easily implement Fast DMA interface in close comparison to the PC's ultra DMA.

For the USB, I would be very careful, even thought TI says it supports full USB high speed interface, in reality I don't think you can get more than 300Mb/s at most.

I used to work at TI as level 2 support for their OMAP products before they cut off their staff in France and got rid of almost all contractors (me included), if you give more details about your projects and your need, I maybe able to help you with your project.

Cheers,
/Farhad Abdolian

 

[manu.s]

Thank you very much for your prompt response.

We are planning to make this a product.

So the solution involving the PATA controller in a CPLD and PATA/SATA converter seems to be a better choice for maximum throughput.
The basic block diagram showing this interface (as per my understanding) is attached below.
My current understanding/queries regarding this interface are listed below.

• For higher data transfer speed with ATA interface, Ultra DMA mode of operation is required.

• How the OMAP35xx system DMA can be efficiently used in close comparison with Ultra DMA? Do the ultra DMA protocol to be implemented in the CPLD?

If this is the case, do an efficient buffer management possible with a CPLD?

• What will be the maximum through put possible for PATA with this interface? Is this limited by the IO bus speed of OMAP 35xx?

Please comment on these queries.

Thanks & regards
Manu

 

[farhada]

Hi Manu.s,
I am afraid I can not answer to your detailed question that easily.

I don't think it will be cust effective to implement the uDMA in a CPLD. since you need a lot of memory and logic to do so.

The GPMC has an internal FiFo that will be useful for your purpose here. One way to fix your problem will be to make the CPLD so it acts like a memory and then you can use the maximum bandwidth of the SDMA interface and/or using the GPMC's Synchronous Multiple Burst data mode.

I think you can calculate the possible maximum bandwidth if you look into the GPMC interface in the TRM of the OMAP35xx.

One silly solution is to use a OMAPL1xx as your SATA slave which is a much more expensive and more complicated solution, but gives you much more freedom and CPU power.

Best regards,
/Farhad Abdolian

 

[bobcat1]

Hi

Look at ACTEL site for low cost FPGA they have plenty of core suit for there low cost FPGA

Some of the core are given for free and all you need is to use the ACTEL FPGA in your design, a solution that might cost you less then 1$ per unit in the production line

All the best

Bobi

The microcontroller specialist