How to optimization of setup and hold time

[Sahil]

hi all...........

can any body tell me that how can i optimize setup and hold time violation in my layout. plz describe me in detail.

thankyou

regard
shadab

 

[anjali]

to avoid hold violation, insert buffers/inverters in that path.

to avoid setup violation, restructure the design such that the critical path will have less delay, or reduce the operating freq.

in general, we should have setup clean prelayout design. hold violations may automatically reduced in P&R stage.

 

[Sahil]

Hi Anjali........

Thankyou very much for the reply...........
but i hv a little doubt i think we used buffer and inverter insertion technique for setup time optimazation not for hold time .....plz make it clear to me..........
and i also want to know that how software will optimize setup time by buffer and inverter insertion...

waiting for ur reply

regards
sahil

 

[anjali]

Hi Sahil,
Set up time violation occurs if the total delay between the reg. and reg. is more than the clock period.
Total delay = Tcq + TcombMax + Tsetup(Destination Reg.)

If set up violation occurs we need to decrease TcombMax or need to increase the clock period. ( we can not change Tcq or Tsetup values, these are technology dependent)

Hold violation occurs if (TcombMin + Tsetup) < Thold

To avoid hold violations we need to increase TcombMin.

From these we can say that we need to add buffers or inverters to avoid hold violation and we need to reduce the TcombMax to avoid set up violations.

Anjali

 

[coolrak]

Hi anjali,

I am having a different view for your point on hold time. If you use buffers(with high drive strength) in the data path, you are improving the timing and there are high chances of violating the hold condition.

Infact thats the reason while we do STA we use best case conditions for checking the Hold condition.

These are my views and correct me if I am wrong

 

[anjali]

Hi Collrak,
What you said is correct. But that depends on the buffer selection.

If we add high drive strenght buffers definetly timing will improves. so path delay gets reduced. But the tool will selects the buffer strength optimally such that hold violation will not occur. Tool will take care for that.