how to obtain very large resistors

[safwatonline]

what is DMOS??!

 

[andy2000a]

DMOS is double diffusion mos for high volt using
device is different standard CMOS

CMOS usually use "LDD" in drain/source, and it cause Rsh (drain source resistor) too small , and some Hi-V mos process remove LDD
for improve breakdown/ESD .. and large Ron

but , as I know , DMOS use driver large power
some fab will small Ron

 

[horzonbluz]

No, I mean use diffuse NMOS not double diffusion MOSFET.

 

[safwatonline]

NMOS has higher mobility than PMOS i.e. lower resistivity and hence lower Ron

or is the diffuse NMOS something diffrent plz clarify more

 

[jeff_zx]

low implanted poly silicon

 

[srivatsan]

One thing: When using meandering layout, the current path crowds near the corners. The effective resistance is just too tough to know. Also remember that poly will be coupled to the substrate. Capacitance is a Big problemo!!

I would re-jig the circuit to reduce this resistance.

I would try to avoid using any active devices ... because it is frequency dependent.. again you got to do frequency modeling and all sorts of other parameters...It is an unwiedly number. There is only one way to know. Do a test chip fab. Also do only long straight lines. Cannot help it.

Now, if you dont really have "appropriate" space (not that you wouldnt have enough space), then break the resistor into (say) 20 50kΩ resistors. Then put them in "parallel" form and then join them using metals. But Now you got more variabilities.. like contact resistance,etc..

Also note one thing, if you use 1MΩ, then presence of about 10pF can alter your frequency characteristics, not to mention previously stated heat-dissipation.

Personal Experience: I made a test chip with lots of resistors and caps. I did 750kΩ, to 2.5MΩ. I got numbers all around the map. It works okay but I would avoid using such numbers.. Caps are better in their performance... Again all my comments depends upon the fab. I worked on 0.5um.

Try to "re-jig" it..

Srivats