happsky
Advanced Member level 4
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 MULT_ADD U_MULT_ADD( .clock0(clk), .dataa_0(Ch_reverse[15:0]), .dataa_1(Ch_forward[15:0]), .datab_0(K_reverse[7:0]), .datab_1(K_forward[7:0]), .ena0(GATE), .result(sub_result[24:0]) ); reg [4:0] delay_GATE; always @(posedge clk) //Four clock of delay, How to know MULT_ADD'delay is 4 clock ? delay_GATE[4:0]<={delay_GATE[3:0],GATE}; wire ageb; sign_comp U_sign_comp( .clken(delay_GATE[3]), .clock(clk), .dataa({5'd0,SP_P[15:0],4'b0000}), .datab(sub_result[24:0]), .ageb(ageb) );
Could anyone tell my that why the delay of Mutl_ADD is 4 clock. thank you very much!