How to insert iprobe and still can pass LVS?

[bageduke]

Hi,

I am running DC simulation for very large schematic to check leakage current/active DC current from each sub-blocks. (many of them share same power supply)

Normally, in Cadence, people insert a VDC on top of each supply for every block so that they can see how the current is divided to each sub-block. The problem for me is that if I insert VDC in schematics, circuits cannot pass LVS.

If I copy those schematics to other views in cadence, it will become very hard to maintain consistence between real schematic(the one matches layout) and simulation schematic.

Is there iprobe which I can just insert into each schematic and can be seen as short in LVS?

Thanks a lot!

 

[dick_freebird]

If you use a presistor, that can be probed the same as a source
but for LVS it netlists as a short.