How to improve the load transient response for regulator

[Analog_starter]

Hi all,

Anybody can tell me how to reduce the undershoot when there is coming a peak current loading on a voltage regulator output? Is it only I can do just add output node capacitance as big as possible? Please help me. Thanks!

Regards,
Analog_Starter

 

[edwintsu]

What type of voltage regulator, Linear or switching?

 

[Analog_starter]

Hi, edwintsu,

Just a Linear regulator. like a LDO. But I just need max output peak current is 20mA, it is a VDC.

 

[edwintsu]

Maybe you need refine ur compensation parameters for all loads.

 

[Analog_starter]

No, I mean what's the main factor to limit the load transient response performance? I find the drop voltage is big when there is a current loading peak.

 

[edwintsu]

Sorry, i'm wrong.
U need refer to the technical file from TI.

 

[Analog_starter]

Thank you, edwintsu.
Is there any methoed for fully on-chip design without big off-chip bulky capacitance?

 

[edwintsu]

U can refer to Milliken's LDO. It works well at the low voltage.
'Full on-chip CMOS LDO' Easy found in the forum.

 

[Analog_starter]

Thanks, one more, how to enlarge the colsed loop bandwith? And improve the slew rate of error amplifer?

 

[quaternion]

Thanks, one more, how to enlarge the colsed loop bandwith? And improve the slew rate of error amplifer?

Yes ,these 2 factors are the factors that control the load transient response.

Before applying the compensation scheme your loop GBW - & some times EA SR- is of good value but depending on the compensation scheme the dominant pole and so the GBW is affected also the SR could be degraded as well.So you should select the suitable compensation scheme that lesser reduce GBW & SR and so the transient response.

 

[Analog_starter]

Thanks. How about the one stage folded cascode op for the EA and cascode miller compensation? Is it better than normal two stage EA for the good load transient reponse?