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Vt ln(7) is PTAT and Vbe is CTAT isnt it. So adding them should give you zero TC at some current value. Of course one needs to tweak a bit to get the exact value as in any design.
HFPSRR is primarily about controlling the pass-FET's gate.
It needs to be stiffly coupled to the high side rail or you
will get direct multiplication of power supply noise. At low
power / low current in the gate driver circuit, you lose the
shunting impedance to stand that off, and you probably
also have capacitances to ground in the high-side current
mirror / level shifter legs that inject supply noise. This
latter, you might comp by properly sized explicit capacitors
to VIN or GND at strategic points. Using Miller comp across
the output FET can also help kill the gate-node sensitivity
locally.
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