How to implement Divisio Function on Xilinix V4 ?

[omara007]

Hi folks

I am trying to implement a division function on Xilinx V4. What I know is that only multipliers are built in. In other words, it's unlike ASIC in which I can pull a DW component for the multiplier.

Does anyone have a work around designing dividers in FPGAs without having to actually code up a divider by hand ?

 

[sameem_shabbir]

There is an IP core available in Xilins ISE Core Generator with the name of "Pipline Divider" or "Divider generator" in MATH Function category.

However disadvantage is that code is not visible.