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Hi
You can convert the gated clock with the help of the syunthesis tool like synplicity and you have the option that can convert the gated clocks. Alternatively you can go to the code that has the gated type of coding and you can recode it so that the clock is not gated with respect to other signals
Hi,
I face the gated clock's problem even though i use the synplify's option helping get rid of the clock. After place and route in Xilinx, the tool shows there are several gated clocks. I think the option does not work.
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