javierh.santiago
Junior Member level 2
Hello everyone,
After generating the netlist of my circuit with Design Compiler, I proceed to generate the VCd file in modelsim in order to obtain the power estimation with Prime Time PX. My problem happens when I generate the vcd file as I am running out of space in the HDD. My question is, Do i need to dump all the signals as below command in order to estimate the power?
vcd add –r [name_testbench]/uut/*
Despite it´s a simple uut and the simulation needs to run for 20mS, the vcd files needs 55Gb of space for only 8.5ms. Could you advice on this?
-Francisco
After generating the netlist of my circuit with Design Compiler, I proceed to generate the VCd file in modelsim in order to obtain the power estimation with Prime Time PX. My problem happens when I generate the vcd file as I am running out of space in the HDD. My question is, Do i need to dump all the signals as below command in order to estimate the power?
vcd add –r [name_testbench]/uut/*
Despite it´s a simple uut and the simulation needs to run for 20mS, the vcd files needs 55Gb of space for only 8.5ms. Could you advice on this?
-Francisco