avinashch
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i am trying to generate test pattern for the full adder but i am not getting anything out of it. it is reading the netlist but not giving any results.
it is giving N5 warning.
at the end of reading the netlist it gives
#modules=0, top-full_adder, #lines=29, cpu time=0.00 sec, memory= 0mb
is there anything else that i need to do to make it work??
here is my code for the adder:
module full_adder(input1,input2,carry_in,sum,carry_out);
input input1;
input input2;
input carry_in;
output sum;
output carry_out;
wire int1_sig;
wire int2_sig;
wire int3_sig;
assign int1_sig = input1 ^ input2;
assign int2_sig = input1 & input2;
assign sum = int1_sig ^ carry_in;
assign int3_sig = int1_sig & carry_in;
assign carry_out = int2_sig | int3_sig;
endmodule
the testbench is as follows:
module test_adder_1bit;
// Inputs
reg input1;
reg input2;
reg carry_in;
// Outputs
wire sum;
wire carry_out;
// Instantiate the Unit Under Test (UUT)
full_adder uut (
.input1(input1),
.input2(input2),
.carry_in(carry_in),
.sum(sum),
.carry_out(carry_out)
);
initial begin
// Initialize Inputs
input1 = 0;
input2 = 0;
carry_in = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
input1=1'b0;input2=1'b0;carry_in=1'b1;
#10;
input1=1'b0;input2=1'b1;carry_in=1'b0;
#10;
input1=1'b0;input2=1'b1;carry_in=1'b1;
#10;
input1=1'b1;input2=1'b0;carry_in=1'b0;
#10;
input1=1'b1;input2=1'b0;carry_in=1'b1;
#10;
input1=1'b1;input2=1'b1;carry_in=1'b0;
#10;
input1=1'b1;input2=1'b1;carry_in=1'b1;
end
endmodule
it is giving N5 warning.
at the end of reading the netlist it gives
#modules=0, top-full_adder, #lines=29, cpu time=0.00 sec, memory= 0mb
is there anything else that i need to do to make it work??
here is my code for the adder:
module full_adder(input1,input2,carry_in,sum,carry_out);
input input1;
input input2;
input carry_in;
output sum;
output carry_out;
wire int1_sig;
wire int2_sig;
wire int3_sig;
assign int1_sig = input1 ^ input2;
assign int2_sig = input1 & input2;
assign sum = int1_sig ^ carry_in;
assign int3_sig = int1_sig & carry_in;
assign carry_out = int2_sig | int3_sig;
endmodule
the testbench is as follows:
module test_adder_1bit;
// Inputs
reg input1;
reg input2;
reg carry_in;
// Outputs
wire sum;
wire carry_out;
// Instantiate the Unit Under Test (UUT)
full_adder uut (
.input1(input1),
.input2(input2),
.carry_in(carry_in),
.sum(sum),
.carry_out(carry_out)
);
initial begin
// Initialize Inputs
input1 = 0;
input2 = 0;
carry_in = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
input1=1'b0;input2=1'b0;carry_in=1'b1;
#10;
input1=1'b0;input2=1'b1;carry_in=1'b0;
#10;
input1=1'b0;input2=1'b1;carry_in=1'b1;
#10;
input1=1'b1;input2=1'b0;carry_in=1'b0;
#10;
input1=1'b1;input2=1'b0;carry_in=1'b1;
#10;
input1=1'b1;input2=1'b1;carry_in=1'b0;
#10;
input1=1'b1;input2=1'b1;carry_in=1'b1;
end
endmodule