How to generate a clock of 64KHz from FPGA in vhdl?.

[xtcx]

generate clock vhdl

Guys for my project I need to use a 64KHz and 2048KHz clock for codec as its bit clock. So how can we divide and get 64KHz\2048KHz from 80MHz system clock in Xilinx Virtex4 FPGA. I know a lot of clock divider has already been described, but I still can't get a clear fact,most of the divder programs usually don't generate 50% duty cycle or rather not working. For my part 50% duty is important.Got any ideas?, plz share. Thanks in advance.

 

[craftor]

how to generate a clock

Hers is an easy example about clock division which is 50%duty cycle, hope it will help you . Craftor

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity clkdiv is
generic ( n : integer :=10);
port (
clkin : in std_logic;
clkout : out std_logic);
end clkdiv;

architecture arc of clkdiv is
signal clk_tmp : std_logic := '0';
signal cnt : integer := 0 ;
begin
process (clkin,cnt) begin
if (clkin'event and clkin='1') then
cnt <= cnt + 1;
if ( cnt = n-1 ) then
clk_tmp <= not clk_tmp;
cnt <= 0;
end if;
end if;
end process;
clkout <= clk_tmp ;
end arc;

 

[xtcx]

vhdl generate clock

Yeah!, thanks for your approach craftor, but the divider program although provides 50% duty cycle but still how can you get the desired freq of 2.048 MHz from a 20MHz?. If you divide the clock of 20MHz by 10, then you should get 2MHz not 2.048MHz.But I want to get 2.048 MHz or 2048 KHz clk from an input clk of 20MHz. Do you understand my case?.

 

[avimit]

how to generate a clock signal in vhdl

I dont think that what you want can be done using a pure digital logic design. Since the frequency you want is not a factor of the frequency you have, I am almost certain that you need some thing else than digital logic.
64Khz shouldn't be a prob from 80Mhz as 80Mhz/64Khz is a whole number and that too even, so you will and can get a 64Khz clock from 80Mhz clock with 50% duty cycle using pure digital logic design
Kr,
Avi

 

[craftor]

how to generate a 2 khz from a 1 mhz using vhdl

Agreed with Kr,Avi.
The codes I have given above is just an example, if you want to get 64KHz, you have to write the codes by yourself.

GL!
Craftor

 

[penrico]

generate clock in vhdl

You can try divide in 4 steps.

First step divide by 9. The other 3 steps divide by 10.

The general division ratio will be:

(9+10+10+10)/4 = 9.75

So, if you have a 20Mhz clock

ClkOut = 20Mhz/9.75 = 2051 Mhz

Here you have how to do it, I don't test it. Please reply what do you think


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity clkdiv is
port (
clkin : in std_logic;
clkout : out std_logic
);
end clkdiv;

signal subcount : std_logic_vector[2 downto 0];
signal count: std_logic_vector[3 downto 0];
signal clk_tmp : std_logic;

architecture arc of clkdiv is
begin

process (clkin) begin
if clkin'event and clkin='1' then
if (count<9 and subcount=0) or (count<10 and (not subcount=0)) then
count<=count+1;

else
count<=(others=>'0');
clk_tmp<=not clk_tmp;

if (subcount<3)
subcount<=subcount+1;
else
subcount<=(others=>'0');
end if;
endif;
end if;
end process;

clkout <= clk_tmp ;
end arc;

 

[FvM]

generating clocks using vhdl

Your suggesting a fractional divider. It may be solution if some additional clock jitter can be tolerated. We can't know, as no quality specification was given.

 

[jamesbowman]

Re: generating clocks using vhdl

This page explains fractional clock division, and gives the VHDL and Verilog to do it.

Making an arbitrary frequency clock in VHDL and Verilog

in this case your input frequency is 80000000 and output frequency is 2048000.

You can derive the 64KHz from the 2048KHz by a simple divide-by-32.

 

[jimmy_tag]

VHDL code for Clock Divider

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

entity sec_clk is
Port (
Clk : in std_logic;
rst: in std_logic;
op : out std_logic
);
end sec_clk;

architecture RTC of sec_clk is
constant max_count : natural := 24000000;
-- I used 24MHz clock

begin

compteur : process(Clk,rst)
variable count : natural range 0 to max_count;
begin
if rst = '0' then
count := 0;
op <= '1';
elsif rising_edge(Clk) then
if count < max_count/2 then
op <='1';
count := count + 1;
elsif count < max_count then
op <='0';
count := count + 1;
else
count := 0;
op <='1';
end if;
end if;
end process compteur;
end RTC;


the above code generates 1sec i.e. 1Hz o/p.
If you have 80MHz clock. then to divide it to 64KHz you can do following

i.e. if max_count=80000000 produces 1Hz clock from above code with 80MHz i/p then

80000000 = 1sec
x = (1/64000)sec i.e 15.6µs


then x=1250

u will get the perfect clock of 64KHz freq and 50% duty cycle. if you set max_count to 1250. with i/p clock of 80MHz.
You can set the duty cycle by changing the 'y' value in (max_count/y) in process.
Similarly you can set max-count=39 for 2048Khz clock o/p.