How to do q <= d[count:0] in Verilog?

[woeichee]

in verilog, how to do like q <= d[count:0]?

reg [3:0] count;

thanks

 

[shitansh]

Re: Verilog

reg [3:0] count;;
reg [15:0] q;
wire [15:0] d;

always @ (posedge clk or negedge rst_n)
begin
if (~rst_n)
q <= {16{1'b0}};
else
q<= d[count:0];
end

HTH,