How to do IO signal delay in FPGA

[vivizzz]

hey guys,

Im new to FPGA. got some problems about the output delay. I got two output signals, A and B. I want B is a little bit delay than A, like 1 us. I write the delay code in verilog code, the behavioral simulation result is good. But when I download the code to the FPGA borad and using the scope detecting the signals, there is no delay. Is anything I can do to get the output signal delay?? Thanks



vivi

 

[permute]

Re: IO delay in FPGA

for that scale you almost certainly have to move to oversampled outputs. Eg, if an interface sends serial data with a clock, at a rate of 1Mbps, you could provide the module with an 8MHz clock. the output of the module would change only once per 8 cycles. now a variable number of registers can be inserted between the module, and the IO. The number of registers between the modules "serial clock output" and the FPGA's IO pad is intentionally made different than the number between "serial data output" and the FPGA IO pad.

 

[vivizzz]

Re: IO delay in FPGA

hey permute:

thanks for the reply. Im actually working on generating the PWM signal, require for the adjustable frequency and dutycycle. The tiny delay between two output should be adjustable too. but.... i didn't even get the delay!

thanks again.

 

[rberek]

Re: IO delay in FPGA

Delays are not synthesizeable.

r.b.

 

[hafeez]

Re: IO delay in FPGA

rightly said, delays are not synthesizeable........... U have to pick some clock cycles to produce delays!

 

[mahdiksh]

i work on vhdl in that language delay not synthesizeable.

for your work with known main signal frequency. you can count the main clock to give 1us then release THE OUTPUT.