vivizzz
Newbie level 3
hey guys,
Im new to FPGA. got some problems about the output delay. I got two output signals, A and B. I want B is a little bit delay than A, like 1 us. I write the delay code in verilog code, the behavioral simulation result is good. But when I download the code to the FPGA borad and using the scope detecting the signals, there is no delay. Is anything I can do to get the output signal delay?? Thanks
vivi
Im new to FPGA. got some problems about the output delay. I got two output signals, A and B. I want B is a little bit delay than A, like 1 us. I write the delay code in verilog code, the behavioral simulation result is good. But when I download the code to the FPGA borad and using the scope detecting the signals, there is no delay. Is anything I can do to get the output signal delay?? Thanks
vivi