how to display on seven segment display

[Deleted member 368350]

guys can anyone help me how to display on the seven segment display ..this is my cod. I have made a counter using JK flip flops which counts from 0 to 6..I have no idea how to display it on the 7 segment display..can anyone give me a code specific to this code

module counter(
input clk,
input reset,
output a,b,c
);
wire w1,w2,w3;
and(w1,b,c);
or(w2,a,c);
nand(w3,a,b);

jk_ff g1(w1,b,clk,reset,a);
jk_ff g2(c,w2,clk,reset,b);
jk_ff g3(w3,1,clk,reset,c);

endmodule


//module for JK flip flop


module jk_ff(
input j,
input k,
input clk,
input reset,
output reg out,
output out_bar
);
assign out_bar = ~out;
always @ (posedge clk or negedge reset)
if (~reset) out<=1'b0;
else
case ({j,k})
2'b00 : out <= out;
2'b01 : out <= 1'b0;
2'b10 : out <= 1'b1;
2'b11 : out <= ~out;
endcase

endmodule

 

[john blue]

Do something similar to:

case ({j,k})
2'b00 : out <= out;
2'b01 : out <= 1'b0;
2'b10 : out <= 1'b1;
2'b11 : out <= ~out;
endcase

so that you can use the bits to control the 7 segment display or you can also use a seven segment decoder =)

 

[sameh_yassin99]

Hello,
You have to provide information about the hardware that u are using. I've done similar trial using xc2-xl xilinx board which contains Two CPLDS.
I used the smaller CPLD for operation (XC9572XL). I used 8 pins of the board to connect directly to the 8 leds in the seven segment (including the led of decimal point). Obviously it is not hardware efficient but I was just making a trial so I didn't pay much attention for the wasted 8 I/Os on simple display.
Here is the code I used and it worked very well
P.S.:
* I use the satndard names of 7-segment display (a, b, c, d, e, f, g, dp)
* My 7-segment is common anode so I send 0 to the led so that it lights
* My crystal oscilator is only 1 MHz, if u use faster crystal you will need use
lager counter or use clock manager if available.

module Display_7Seg (a_out, b_out, c_out, d_out,e_out,f_out,g_out,db_out, Clk_in);            

output a_out, b_out, c_out, d_out,e_out,f_out,g_out,db_out;
input Clk_in;
reg    ctr_8bits;

always @(Clk_in)
     case (ctr_8bits)
        8'h00 :
        -- draw Zero 
        a_out = 0, b_out = 0, c_out = 0, d_out = 0, 
        e_out = 0, f_out = 0, g_out = 1 ,db_out = 1;
        8'b01 :
        -- Draw 1 
        a_out = 1, b_out = 0, c_out = 0, d_out = 1, 
        e_out = 1, f_out = 1, g_out = 1 ,db_out = 1;
        2'b10 :
        -- Draw 2
        a_out = 0, b_out = 0, c_out = 1, d_out = 0, 
        e_out = 0, f_out = 1, g_out = 0 ,db_out = 1;
 
     endcase
endmodule

Try it, and if sthg goes wrong send me ur complete code and I'll try it on my kit.

regards,
S. Yassin