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how to determine the upper limit frequency of pnoise?

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chaojixin

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I want to simulate a delay line's jitter(Jc). this delay line drives the PWM signal of a TDC(that is, its pulse width is to be measured). surpose that the delay line's bandwidth is W1, and the sampling rate of TDC is W2, the TDC's resolution is N bit, the TDC's clock frequency is F3. what is the appropriate lower limit and upper limit of integration frequency? ?

thanks in advance!
 
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