[SOLVED] How to determine the PGA's GBW in the applifcaiton of precision DC signal sigma-delta ADC

[RingFinal]

In a PGA+SD system that converts DC signal. Threre is no problem to trace a DC signal with a 300KHz bandwidth PGA. While with the 1MHz sampling opration of SD's S/H circuits, the ouput of the PGA varies (e.g. ±FS or FS-Vcm) and thus contribute a spike. This spike is even worsed by charge injection. After switching, PGA's output recovers to the voltage it should be. Yeah a delayd sample operation can avoid the sipke's peak, but it still need time to wait the output settles. Is it the feedback loop that recovers the PGA's output ?

1) I was thinking a high GBW of PGA is required to make sure a accurate signal sampled by ADC, while this is power consuming and poor noise perfomance due to alising;
2) If not to relay on the PGA's fast loop to settle the output, ADC's sampled signal would be a divided version of "PGA Rout@Fs" and "1/(2*Fs*Cs)". The PGA's Rout @FS is very hard to control with PVT variation.
3) If there is a considerable large cap (>>Cs) at the PGA's output , this is area inefficient and contribute a gain error.

In many papers or datasheets, I notice the GBW of the PGA is always slower than the ADC's sampling frequency (e.g. PGA's GBW=300KHz, ADC sampling Frequency = 1MHz), in this case how to make sure a accurate signal being sampled? Is there any silly misunderstanding in my above analysis? Could anyone help explain, thank you!

 

[KlausST]

Hi,

What you describe is typical amplifier ringing behaviour on output step.
Surely this is caused by the amp's feedback.
A bigger C at the output can improve this, even better a RC.

Now you say GVW of the amp is less than sampling frequency. I wonder ... but maybe this is the case.

In either case:
The ringing should be rather high frequency, thus it should cause ignorable AC error after the digital filter.
But the ringing is triggered synchronously to the sampling frequency, thus there is a chance that it causes DC error after the filter.
DC error can be canceled out by calibration.

Klaus

 

[FvM]

If 1 MHz is the SD (over)sampling rate, I won't expect more than 100 kHz useable bandwidth, possibly less depending on the decimator design. Sufficient suppressing of alias frequencies above fs/2 is however required.

 

[RingFinal]

Hi,

What you describe is typical amplifier ringing behaviour on output step.
Surely this is caused by the amp's feedback.
A bigger C at the output can improve this, even better a RC.

Now you say GVW of the amp is less than sampling frequency. I wonder ... but maybe this is the case.

In either case:
The ringing should be rather high frequency, thus it should cause ignorable AC error after the digital filter.
But the ringing is triggered synchronously to the sampling frequency, thus there is a chance that it causes DC error after the filter.
DC error can be canceled out by calibration.

Klaus

Thank you Klaus, I just simulated the non-linearity, slower PGA mainly contribute gain error, nonlinear error is ignorable.

--- Updated Dec 23, 2021 ---

If 1 MHz is the SD (over)sampling rate, I won't expect more than 100 kHz useable bandwidth, possibly less depending on the decimator design. Sufficient suppressing of alias frequencies above fs/2 is however required.

Thank you FvM, I have another question about "useable bandwidth" if you are willing to explain...

For a PGA configured below (macro model), the overall bandwidth from source to output is limited by Cf*Rf, which is about 158KHz, while the OPA Loop is very fast ( STB.PhaseMarginFre=158M). In this way output settles very fast during S/H circuits switching, while drawback is the 158kHz-Filter cannot suppress the OPA's noise well. The second figure indicate a poor SNR, maybe NoiseFigure is more accurate.

Although fast OPA leads more alising noise (total noise), more current means low noise density hence total noise may not that high. So the useable bandthwith is used to limit the source, or the total outputs. So...how do you understand this?

 

[FvM]

I related useable amplifier bandwidth primarily to the decimated ADC signal and mentioned, that aliasing signal components must be filtered before the SD sampler.

Amplifier (and also sampling switch) noise is an additional problem. I'd talk about excess amplifier bandwidth in this relation. I take from your previous remarks that a low-pass filter between amplifier and sampler is no option for the design. So amplifier bias and sampler bandwidth are the only parameters to tune noise.