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How to design PWM discriminator circuit?

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vicente_ly

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hi everyone, im a new fish in analog field form sweden.

these is a project for me rightnow to desgin a CMOS discriminator circuit for data and clock recovery of the PWM signal.

However i don't know much about it . So can some nice guys give me some hints or recommend some valuable materials to me?

Thanks a lot.
 

Dear vicente_ly :

Do you want a CDR circuit for your data and clock recovery ?
If yes, you can find some informations in WWW.
If no, please detail to discuss your spec for your circuit.


mpig09
 

thanks for your reply,mpig09

for a given PWM signal , 0 and 1 are presented with short pulse and wide pulse respectively.

then i need to design a cmos recevier circuit which is utilized to distinguish width difference and extract the data and clock.

so i think may be a CDR cirtuit is needed .

could u please rewrite the website again whichi is not shown correctly in ur reply.

Best regards.

Vicente
 

Hi Vicente,
I am also looking for the same solution. Thus, not sure if you have that CDR website for reference ?

Thank you.

Peter
 

One of the methods I use is by sending pulses of the same period but with a different duty cycle for 0 and 1 ?
 
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    pkung

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Thanks for Kerimf's reply.
Since the period of the received PWM may vary within the fixed range (ex: 3Mbps ~ 9Mbps) and the period can not be predicted prior , I am looking for an idea to extract the clock and data from the received PWM .....
 

Thanks for Kerimf's reply.
Since the period of the received PWM may vary within the fixed range (ex: 3Mbps ~ 9Mbps) and the period can not be predicted prior , I am looking for an idea to extract the clock and data from the received PWM .....

I usually work in rather low speed links to send data to refresh some LED displays for example. On the other hand, I had to design all parts of a new system; hardware, firmware and system protocol as well, since I can't get easily the tools/components and utilities/programs as most of you. So I used to work with standard ICs and ATMEL C51 MCUs (programming them using assembly on DOS).

I think, for high frequencies, there must be a variety of ICs for this job. At low frequencies things are much easier ;) It just needs a sort of monostable (hardware or software) and its trailing edge latches the bit data. In your case if the received signal period is not known in advance, an initial synchronization should be added (by software is easy, in hardware it may need a special IC).
 

Thanks for input again. :)
 

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