chmhero
Member level 1
design a intege N synthesizer.
reference clock 50K
bandwidth 5KHz(big cap in chip).
N =1000 above
i set the Icp to 5uA, sb tell me the leakage current is so much, and the leakage curren will generate the spur , how to estimate the spur? how to design the PLL with less spur.
any advice is welcome .
reference clock 50K
bandwidth 5KHz(big cap in chip).
N =1000 above
i set the Icp to 5uA, sb tell me the leakage current is so much, and the leakage curren will generate the spur , how to estimate the spur? how to design the PLL with less spur.
any advice is welcome .