Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
you mean the input frequency or the sampling frequency, be careful about this, this is related to OSR.
you can use the general design methodology about sigma delta modulator. if it is the input frequency, I think 2 stages - single bit one may be a good choice.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.