How to decrease the delay of an inverter

[abcyin]

inverter min delay

Hi, all

I need to decrease the delay of an inverter, I know that I can decrease the delay by increasing the width of NMOS and PMOS transistors, thus increasing the gain of NMOS and PMOS, however, this will cause spikes at the output when input switches between one and zero. so is there any other method to decrease the delay?

Thanks in advance.

 

[sear]

decrease capacitance in inverter

use minimum L and decrease loading capacitance of the inverter.

 

[abcyin]

avoid inverter current spike

Thanks for your reply, but already minimum L for the inverter, and the load is a DFF, which also use the minimum size, so any other idea is welcome?

 

[Dr_Libelulix]

delay using inverters

You cannot decrease the delay time of the inverter and avoid parasitic spikes if you are using the minimum lenght and large widith. If you are concern of the spikes try to reduce the current supplied to the inverter by using a current source. This will decrease the time response of the inverter.

 

[diemilio]

negative postive edge delay

You cannot decrease the delay time of the inverter and avoid parasitic spikes if you are using the minimum lenght and large widith. If you are concern of the spikes try to reduce the current supplied to the inverter by using a current source. This will decrease the time response of the inverter.

Yes you can... it's not only a matter of making your inverter larger and larger. There's a limit to this. The way around it is cascading a series of inverters each of which is a certain value larger than the previous one. You can find the derivation of this method in almost any CMOS digital design book. I like Rabaey's approach.

Check chapter 5 of "Digital Integrated Circuits A Design Perspective" by Jan M. Rabaey. The section is called "Sizing a chain of inverters"

Hope this helps,

diemilio

 

[erikl]

how to minimize delay in inverter

... the load is a DFF, which also use the minimum size, so any other idea is welcome

DFFs usually contain an internal clock inverter. Take or create a DFF which works with the other clock edge.

 

[abcyin]

... the load is a DFF, which also use the minimum size, so any other idea is welcome

DFFs usually contain an internal clock inverter. Take or create a DFF which works with the other clock edge.

I am not very sure about your suggestion, for example, now I am using the positive edge trigger for DFF, then you suggest to use the negative edge trigger, could you explain the difference? Why can it decrease the delay?

 

[erikl]

... now I am using the positive edge trigger for DFF, then you suggest to use the negative edge trigger, could you explain the difference? Why can it decrease the delay?

If I understood you correctly, I think you want to minimize (or even save) the delay of an inverter? I guess it's the clock inverter? This would mean, your inverter input gets the negative active clock edge, its output provides the positive active clock edge to the DFF clock input, right?

(If it were a setUp or hold pb., i.e. a delay pb. of an inverter in front of the data input, you could always choose to use the inverted clock, or save the data inverter and use a DFF with both Q and Qbar outputs.)

Because a DFF (internally) always needs both edges, it always contains an internal clock inverter. So it is possible to design DFFs with either positive or negative clock edge control, with the same timing wrt. the controling clock edge. Rich foundry libraries offer both types of DFFs with practically identical timing. If not available, you could perhaps design your own one; only few changes are necessary.

And that's what I meant: in this case you wouldn't need the inverter in front of the DFF. ;-) Hope, I got you right!

 

[vinayakbhat82]

Increasing the inverter width might decrease the delay of the current stage. However, please note that this larger inverter would present an increased load to previous stage which might increase your total delay.

Also, I do not understand the reason behind seeing spikes with inverter with greater width. Can anybody please help me understand?