swkimaz
Newbie level 6
How to decide offset frequency in phase noise?
Hi,
I have relaxation oscillator(ROSC) as reference clock for PLL. Based on PSS/Pnoise simulation of ROSC, I have ~3ns of RMS jitter if I integrate phase noise from 1KHz to 1MHz of offset frequency. Most of them are contributed by below 100KHz of offset frequency and PLL does not care of this phase noise because its bandwidth is larger than 100KHz. This clock will be used for ADC sampling through PLL.
Now, here are my questions.
1) For communication system application, we will have offset frequency for phase noise in system specification. But for microprocessor, memory, or ADC clock, how do I decide offset frequency range to integrate phase noise to calculate jitter? Should I integrate phase noise from low offset frequency(~1KHz) to ADC sampling frequency? If so, what is criteria to select it?
2) I want to add phase noise in ROSC to phase noise of PLL. I did PSS/Pnoise simulation for ROSC only and apply the data of phase noise of ROSC to close loop transfer function of PLL in Matlab. I know this is one of reasonable ways to see phase noise of reference clock in PLL loop. But, phase noise from simulation(PSS/Pnoise) has a unit of dBc/Hz and meaning is that x-axis of phase noise starts just offset frequency from oscillation frequency(not 0,or dc), but PLL transfer function has different unit(dB), meaning is that response of this function does not start from oscillation frequency. For example, oscillation frequency is 8MHz, PLL BW=1MHz. If we put phase noise of ROSC and PLL transfer function on same plot, reference signal including phase noise will be filtered out by PLL. Is this right simulation to see how does phase noise of reference clock(ROSC) with PLL loop affect to total jitter?
I am looking for your helps.
Hi,
I have relaxation oscillator(ROSC) as reference clock for PLL. Based on PSS/Pnoise simulation of ROSC, I have ~3ns of RMS jitter if I integrate phase noise from 1KHz to 1MHz of offset frequency. Most of them are contributed by below 100KHz of offset frequency and PLL does not care of this phase noise because its bandwidth is larger than 100KHz. This clock will be used for ADC sampling through PLL.
Now, here are my questions.
1) For communication system application, we will have offset frequency for phase noise in system specification. But for microprocessor, memory, or ADC clock, how do I decide offset frequency range to integrate phase noise to calculate jitter? Should I integrate phase noise from low offset frequency(~1KHz) to ADC sampling frequency? If so, what is criteria to select it?
2) I want to add phase noise in ROSC to phase noise of PLL. I did PSS/Pnoise simulation for ROSC only and apply the data of phase noise of ROSC to close loop transfer function of PLL in Matlab. I know this is one of reasonable ways to see phase noise of reference clock in PLL loop. But, phase noise from simulation(PSS/Pnoise) has a unit of dBc/Hz and meaning is that x-axis of phase noise starts just offset frequency from oscillation frequency(not 0,or dc), but PLL transfer function has different unit(dB), meaning is that response of this function does not start from oscillation frequency. For example, oscillation frequency is 8MHz, PLL BW=1MHz. If we put phase noise of ROSC and PLL transfer function on same plot, reference signal including phase noise will be filtered out by PLL. Is this right simulation to see how does phase noise of reference clock(ROSC) with PLL loop affect to total jitter?
I am looking for your helps.
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