how to create simulation files using Cadence SOC Encounter ?

[rui_yang]

Hi all,
I'm a student learning to use Cadence SOC Encounter to generate necessary files which will be used in Nanosim simulation. I can get the verilog netlist file and .spef after P&R using encounter. How can I get the SPICE models file(.mod) ? Do I need some other files when I'm going to use Nanosim to perform transistor-level simulation ? How can I perform Nanosim simulation using these files?

Please help, I am new using these tools.

 

[rca]

as the step to do the LVS, you need to transform the verilog netlist in spice netlist.
first remark, simulate a full netlist in spice + RC could be very long.
there is some tool like "v2lvs" used to transform the verilog into spice and you need to provide the spice model of all your macros /std-cell used in the verilog netlist.