how to count clock cycles ?

[tom_hanks]

hi,
In my application I need to consider signal ACK valid only if its active for five clock cycle..

now how can I write VHDL for this..?
do I have to count clock always after assertion of ACK signal?

pls help me..
tom

 

[leonyang]

You can assert a small 3-bit counter to monitor sigal ACk.

 

[OvErFlO]

signal count : std_logic_vector (8 downto 0);
valid :std_logic;

valid : process (clk)
begin

if (rising_edge(clk) AND ack = 1) then
count = count +1;

if count < 5 then
valid <= '0';
else
valid <= '1';
end if;

end process Valid;

I think that it's not perfect but it's a idea

 

[tom_hanks]

cheers maye..
can i say something..
i heard that its not good design practise to count clock..
thats why im bit confused..

i dont know why it is not good way..
but if u know pls tell me..

tom

 

[OvErFlO]

I don't understand what do you want say ...

 

[tom_hanks]

i mean, that may be it is not good idea to count clock cycle..

i am doing coding after years,so feeling problems..

 

[OvErFlO]

If you don't count clock ... what do you want count ???? :roll:
if you don't want use primary clock... use a secondary clock ....

 

[OvErFlO]

Or you can use a shifter register with 5 stage with clock input (with a clock enable on ACK signal ), when the edge clock is in the last stage and you ack is HIGH ... you have an ACK for 5 clock edge ...

 

[ashishjindal76]

Hi
Hey man I dont think that there is any problem that u will face with counters. or else u use the shift register. basically u need to have a delay for 5 clock cycles to get that signal high u can use any method to achive that or simply go for no operation five times or use some other logic where u can spend 5 clock cycles

bye

Ashish