How to convert std_logic_vector to ufixed or sfixed in VHDL?

[melexia]

Hi all,
I am trying to implement DFT in VHDL. My code takes input from memory in std_logic_vector. But if I want to use CORDIC for sin/cos conversion it requires input in 2Qn format. For time being I have arranged bits in that format but is their any function to convert std_logic_vector to ufixed. Because that bit arrngement is going difficult for further operations.
I know that I can use ieee.proposed.fixed library but for that also I will require variables in ufixed or sfixed format.

Please help, time running out off my hands.

Thanks

 

[TrickyDicky]

in the fixed point package, there is a function to convert std_logic_vector to ufixed/sfixed.

function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return UNRESOLVED_ufixed;

there is also a a to_slv function that only takes in a single ufixed or sfixed.

Out of interest, why dont you use sfixed/ufxied for your port inputs rather than std_logic_vector?

 

[melexia]

Thanks, I will definitely try it.
As I am calculating DFT of a signal, input to my code is an output of 8 bit ADC which I will have take as std_logic_vector.
Do u have any suggestion?

 

[TrickyDicky]

the output from the ADC is just an 8 bit signal. You can have the top level as ufixed(7 downto 0) if you want.

 

[melexia]

you r right, i can use it like that.
thanks

 

[Allenlee88]

hi, since i want to do the calculation on multiplying 2 data in fixed point. How i want to write the VHDL? what should i put the library package since i cant use sfixed or ufixed all the time?or any suggestion for the complete VHDL? just a simple multiply 2 data like 1.2 X 3.6

thanks

 

[melexia]

you have to use ieee proposed fixed point library which is available with xilinx ise.
This library allows u to convert std_logic to sfixed or ufixed and reverse.
Also multiplication in fixed point is same as that of in std_logic or integer. use '*' for multiplication.
c <= a * b
all has to be of same datatype

 

[Allenlee88]

Now i am using QuartusII to simulate my VHDL. but i cant run the code successful. there are no respond on Library ieee_proposed; i used. Any suggestion?

 

[TrickyDicky]

Download the VHDL 93 version of the floatfixlib from here:

**broken link removed**

Just include it in your design like any other design file.

the floatfixlib has become a standard part of the VHDL language in VHDL 2008, but vendors are only just starting to support that standard.

but for multiplication, with a pipline register, here is some sample code that synthesises fine in Quartus, even at the top level.

library ieee;
use ieee.std_logic_1164.all;

library floatfixlib;
use floatfixlib.fixed_pkg.all;

entity my_mult is
  port (
    clk       : in  std_logic;
    
    a,b       : in  sfixed(3 downto -4);
    c         : out sfixed(7 downto -8)
  );
  
end entity my_mult;
  
architecture rtl of my_mult is
begin
  
  mult_proc : process(clk)
  begin
    if rising_edge(clk) then
      c <= a * b;
    end if;
  end process;
  
  
end architecture rtl;

 

[Allenlee88]

after go through the link provided, which file i should download? is it consists of 11 files? where should i include those files?
the error said that design library "floatfixlib" does not contain primary unit "fixed_pkg" after run the code.
What to do?

thanks

 

[TrickyDicky]

you only need to include float_fixed_types_c.vhd and fixed_pkg_c.vhd to use fixed point.

Make sure you get the load order correct.

 

[Allenlee88]

sorry for asking this, where or which directory do i need to include that 2 files?

---------- Post added at 23:08 ---------- Previous post was at 23:02 ----------

thanks trickyDicky. i success run the code. going to do the next step. thanks a lot

 

[Bustigo]

can i convert sfixed o std_logic_vector ?

 

[TrickyDicky]

yes
There is a to_slv function

 

[Bustigo]

so if i have a real number should i convert to sfix first then slv

 

[TrickyDicky]

real numbers cannot be used in synthesisable VHDL unless it is a constant.
But yes, real -> sfixed -> slv is easiest.

 

[Bustigo]

thanks i ll use it in testbench only