melexia
Member level 2
Hi all,
I am trying to implement DFT in VHDL. My code takes input from memory in std_logic_vector. But if I want to use CORDIC for sin/cos conversion it requires input in 2Qn format. For time being I have arranged bits in that format but is their any function to convert std_logic_vector to ufixed. Because that bit arrngement is going difficult for further operations.
I know that I can use ieee.proposed.fixed library but for that also I will require variables in ufixed or sfixed format.
Please help, time running out off my hands.
Thanks
I am trying to implement DFT in VHDL. My code takes input from memory in std_logic_vector. But if I want to use CORDIC for sin/cos conversion it requires input in 2Qn format. For time being I have arranged bits in that format but is their any function to convert std_logic_vector to ufixed. Because that bit arrngement is going difficult for further operations.
I know that I can use ieee.proposed.fixed library but for that also I will require variables in ufixed or sfixed format.
Please help, time running out off my hands.
Thanks