how to constraint only limitied areas of a clock signal(ucf)

[vahidkh6222]

hi everyone
I need to know, how can i limit a clock constraint to just limited areas of vhdl codr.
for example i have a clock50M signal for a CIC filter.
i want to constraint nets of the regions before downsampling.
after downsampling there is no longer need to achieve 50Mhz clock efficiency, because the remaining logic works on a rate of 50M/300 (although they have the same clock region, but they have a new_data signal which controls the real rate)

i tried to use different name for the same clock, but xst just removes the different name since they were actually the same...
then how can i constraint only the nets before downsampling (my design is very large so it's very hard to meet 50Mhz constraint for all the nets)

excuse my english, and thanks in advance

 

[childs]

Re: how to constraint only limitied areas of a clock signal(

How about using more than 1 clock signals?

 

[vahidkh6222]

as i said, xst automatically removes equal signals of the different name.

and for some reasond i need these two regions to have the same clock_edge...