How to constraint Differential clock and reset in PXIe-700 including a KINTEX7?

[msdarvishi]

How to constraint Differential clock and reset in PXIe-700 incliuding a KINTEX7 ?

Dear all,


I am using the PXIe-700 Card provided by Sundance including a KINTEX-7 (xc7k410t FFG900) board (more info here). I do not know where are the differential reference clocks location to connect to AXI Memory Mapped to PC Express module in block design? Also, the reset pin location was not mentioned in its User Guide. I always get the following error message in bitstream generation process:

[DRC UCIO-1] Unconstrained Logical Port: 2 out of 3 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: refclkp[0], and refclkn[0].

Can anyone help me to solve this issue? Thanks in advance for your care and consideration.


Bests,

 

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Re: How to constraint Differential clock and reset in PXIe-700 incliuding a KINTEX7 ?

Those are probably the reference clocks for the transceivers that the PCIe is using. If you know the bank the PCIe is on you should easily be able to determine which reference pins are used.

 

[msdarvishi]

Re: How to constraint Differential clock and reset in PXIe-700 incliuding a KINTEX7 ?

Those are probably the reference clocks for the transceivers that the PCIe is using. If you know the bank the PCIe is on you should easily be able to determine which reference pins are used.

Looking at xc7k410t ffg900 packaging datasheet, I found them in BANK 32. Please have a look to the snapshot of refclk and resetn pins. I still get the error. I do not know how to constraint the pins in XDC file?! Thanks for helping me to solve this issue.

 

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Re: How to constraint Differential clock and reset in PXIe-700 incliuding a KINTEX7 ?

I don't know what that utility buffer block is.

I thought the reference clock goes into the PCIe (i.e. the transceiver) block directly. There should have been an option on selecting which one of the reference clocks is used when selecting options for the PCIe. You would then export the block pin to be and external connection.