TCY02
Junior Member level 3
ramp counter vhdl
how to change verilog code to VHDL code
actually the code is like that
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module music(clk, q);
input clk;
output q;
reg [22:0] tone;
always @(posedge clk) tone <= tone+1;
wire [6:0] ramp = (tone[22] ? tone[21:15] : ~tone[21:15]);
wire [14:0] clkdivider = {2'b01, ramp, 6'b000000};
reg [14:0] counter;
always @(posedge clk) if(counter==0) counter <= clkdivider; else counter <= counter-1;
reg q;
always @(posedge clk) if(counter==0) q <= ~q;
endmodule
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how to change verilog code to VHDL code
actually the code is like that
-----------------------------------------------------------------------
module music(clk, q);
input clk;
output q;
reg [22:0] tone;
always @(posedge clk) tone <= tone+1;
wire [6:0] ramp = (tone[22] ? tone[21:15] : ~tone[21:15]);
wire [14:0] clkdivider = {2'b01, ramp, 6'b000000};
reg [14:0] counter;
always @(posedge clk) if(counter==0) counter <= clkdivider; else counter <= counter-1;
reg q;
always @(posedge clk) if(counter==0) q <= ~q;
endmodule
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