How to cause a DELAYED output from a switch (usingFPGA VHDL)

[Peter_L]

vhdl switch led

Hello everyone. I am trying to cause an LED to have a delayed (1 second delay) on / off response to a switch which is being toggled. How do I go about creating this delay using VHDL? I am currently using the Spartan3a development board.

I was thinking of using a 'for loop' to cause the delay, but I am not sure if this is the proper or best way of doing it with an FPGA.

 

[FvM]

vhdl 48bit

Hello,

unlike with an uP, a for loop won't work.

library ieee;
use ieee.std_logic_1164.all;

entity delay_cnt is
	port
	(
		clk	: in std_logic;
		sw	  	: in std_logic;
		led	: out std_logic
	);
end entity;

architecture rtl of delay_cnt is
constant MAX_COUNT 	: integer := 50e6; -- 1 sec with 50 MHZ clock
signal counter 		: integer range 0 to MAX_COUNT;
signal sw_del 			: std_logic;

begin
	process (clk)
	begin
		if rising_edge(clk) then
		   if sw_del = sw then
		      counter <= MAX_COUNT;
		   elsif counter /= 0 then
		      counter <= counter - 1;
		   else
		      sw_del <= sw;
			end if;
		end if;
	end process;
	led <= sw_del;
end rtl;

 

[echo47]

switches and led design in vhdl

Here's another approach. The switch signal passes through a one-second delay-line built from a 48-bit shift register running at approximately 48 Hz. You can rapidly click the switch on and off, and those actions will appear on the LED approximately one second later. ISE implements shift registers very compactly as SRL16 primitives.

I don't speak VHDL very well (sorry!), but maybe you can read this Verilog.
The pin locations and clock frequency are for a different board, the Xilinx/Digilent Spartan-3 Starter Kit.

module top (clk, switch, LED);
  (* LOC="T9",PERIOD="50 MHz" *) input            clk;
  (* LOC="F12" *)                input            switch;
                                 reg       [19:0] count = 0;
                                 reg       [46:0] sr = 0;
  (* LOC="K12" *)                output reg       LED = 0;

  always @ (posedge clk) begin
    count <= count + 1;             // 50 MHz / 2^20 = 47.68 Hz
    if (count == 0)
      {LED,sr} <= {LED,sr,switch};  // switch passes through 48-bit shift register to LED
  end
endmodule

 

[rasj12]

Re: How to cause a DELAYED output from a switch (usingFPGA V

Hello..
{LED,sr} <= {LED,sr,switch}; // switch passes through 48-bit shift register to LED

how the above statement works as shift register?
there is no shift operator in tht statement..

correct me if i'm wrong..
thanks..

 

[FvM]

Re: How to cause a DELAYED output from a switch (usingFPGA V

the bit concatenation and assignment to a shifted bit position works as shift here

 

[echo47]

Re: How to cause a DELAYED output from a switch (usingFPGA V

Let's pretend for a moment that 'sr' has only eight bits.

The 10-bit input word is transferred into the 9-bit output word:

{LED, sr7, sr6, sr5, sr4, sr3, sr2, sr1, sr0, switch}    10-bit input word
       |    |    |    |    |    |    |    |    |
       |    |    |    |    |    |    |    |    |
     {LED, sr7, sr6, sr5, sr4, sr3, sr2, sr1, sr0}       9-bit output word

That's a shift register!

(I shouldn't have put 'LED' into the input word, but it's harmless. The compiler will ignore it.)