how to buffer a clock?

[xtcx]

Hi friends, my design in spartan 3 requires a heavy clock load. The results of par shows clock load of 6000 and even higher with increased logic. I use a single source clk of 40Mhz since all operations need to be synchronous. Hence I use the DCM output <clk_fx> for all loads. My doubt is, if I add another dcm instance and get another <clk_fx>, can I drive my design synchronously?...Will it give the same performance as before?...Or a single BUFG solves my case?...

 

[shitansh]

I think single Clock buffer solve your problem, not forget to give proper constraint for clock.

 

[xtcx]

Well!, thanks shitansh!.
what Clk0 and ClkFx pins do here? when I generate a Single DCM ?....What do they mean by clk0 and clkFx?...Are these clocks same in DCM module?...If I input 20MHz in clk_in of DCM core, will I get same clock outputs at clk0 and clkFx such as 40MHz(I set for this freq) ?....And If I use these two clocks instead of 1 clock, for my operation will it affect in synchronization if values passed from these clocks?.....Please could you clarify me about these clocks in DCM. I need a buffer and is really a DCM needed or should I just use a BUFG instead?....

 

[philoman]

well there are two types of dcm outputs, DLL and DFS.
clk0 is one of the DLL outputs which is of the same frequency as the input reference clock.
clkfx is one of the DFS outputs whose frequency if calculated as fin*M/D, fin is the freq of ref clock, M is the value of CLKFX_MULTIPLY attribute, D is the value of CLKFX_DIVIDER attribute. M&D can be calculated automatically if you tell coregen the desired output freq.

 

[xtcx]

Thanks Philoman, I understand...In my case, I have not set the M and D factor any value(i don't wanna multiply the frq,no need for my design) which means I will get the output of ClkFx the same as clkin right?...So in this case will clk0 and clkFx match each other?. phase? or skew? or etc?....I hope you can figure my question!...thanks again

 

[philoman]

If clkfx is selected as one of the DCM's outputs, you can specify either the output frequency or M/D values according to your design.
If you want clkfx output the same frequency as clkin or if you specify the clkin freq as the output frequency, the M and D will be both set to 2(the min available M is 2), which you can see in the summary page of the Coregen Wizard.
In your case, a BUFG could solve the problem.