how the pt use RC to calculate the net delay?

[bendrift]

which parameter in the lib will affect the net delay calculation after layout?
and how the pt use RC to calculate the net delay?
thank u

 

[eda_wiz]

You can annotate Extracted RC to STA tool to calculate the delay.. time delay could be .69RC if u consider single order R-C network

 

[bendrift]

i want to know more detail process how pt use RC to calculate the net delay.
thank u very much.

 

[eda_wiz]

RC-network is modelled in 3 types..

BEST CASE TREE -- SOURCE IS CLOSE TO SINK.. SO R=0;

WORST CASE TREE - A LUMPED R-C NETWORK
WHERE THE DELAY CAN BE .69RC

TYPICAL CASE: HERE THE R IS DIVIDED DEPENDING ON THE FANOUT.. U NEED TO LOOK INTO TEXTBOOKS TO FIND THE DELAY OF THIS MODEL. SINCE RESISTANCE IS PARALLEL DELAY IS LESSER COMPARED TO WORST CASE TREE

 

[bendrift]

this is calculate by the WLM.
when we back annotate the SPEF/DSPF/RSPF,how do pt calculate the net delay?
thank u

 

[ls000rhb]

i have the same puzzle!
but which tool you use?is it star_rc?
Dose the star_rc only extract the net-delay information except the gate timing information???
i think it can extract a complete spice netlist ,but the spice netlist can be used in the STA tool?
if it is.how the STA work?

 

[bigsnail]

Maybe the answer is in this book:

 

[bendrift]

thank u
it may be useful for me .

 

[RTL2GDSII]

Net delay is determined by the RC of that net. Ther are three model to use :
1. best case : no delay, 2. typical: balanced tree, 3. worst: lumped.PT use the back-annotated parasitic file to calculate net delay according to the model you choose.

 

[bendrift]

i think the three model is used for wlm because the topology is unknow. after layout ,the topology of the RC is knowned,so do pt still use three model?

 

[utmseng]

Have you figured out how pt use RC to calculate the net delay now (not wlm)? If you do, do you mind sharing?