How the delay is incorporated in Verilog synthesis?

[sandeep_sggs]

how the delay is incorporated in synthesis?

 

[srihari_adem]

verilog

Hi,
I think synthesis tool will ignore the delays in RTL..Depends upon ur timing constraints the synthesis tool will pick up appropriate gates from library which accounts for delays.

Thanks
sri

 

[shiv_emf]

verilog

delays r not synthesiable in DC.

It will choose cell n optimize according to constraints