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I think the basic misunderstanding is that the transistor HAS to go through the linear region to go to saturation, which I assume only stems from the usual Id-Vds graph, where the linear region is on the left of the graph. There is no physical reason why the transistor has to go through the linear region. Linear region means there is a channel all along the area between the source and the drain terminals (because the voltage difference between the gate and all points in that area is large enough to form a strongly inverted channel, i.e. larger than Vth roughly). If this voltage difference is not large enough closer to the drain, there is no strongly inverted channel there and the transistor is in saturation. All the saturation state depends on is the voltage difference between the gate and all the points in the substrate between the source and the drain. If you think about it, since the saturation corresponds to part of the area not beeing strongly inverted, physically is a state that occurs BEFORE the existence of a strongly inverted channel everywhere, i.e. the linear region.
Of course to call the transistor saturated you DO need a strongly inverted channel close to the source terminal. That's why (strong inversion) saturation doesn't occur for Vgs<Vth.
One last time...
kgl_13g: You are wrong!
The transistor does go in to saturation without going through linear!
I have writen that several times!
You can see this from the equations, but if the equations are not good enough, then consider this:
What causes the channel to pinch off (causing saturation) and what causes the transistor to begin to conduct are INDEPENDANT! (not really, they are both referenced to the source terminal, but still)
i.e. The condition for channel pinch off can be met BEFORE the device begins to conduct, and if this happens the channel will be FORMED with pinch off at the drain area and will begin conducting in SATURATION!
Can it be any simpler than this?! I don`t get all the back-and-forth.
@ eladla , in the graph you can see clearly at vin=0.7v which is the threshold voltage , the vout starts decreasing with increase in input as the transistor starts entering in to the sat , b/w the points 0.7v to 1.8v transistor is in sat where it satisfies theoritical eqn too VDS >= vgs-vt
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