RRRED
Newbie level 5
Hello,
Can someone point me out how I can read/write to the following blockram RAM model ?
I can read and write to external SRAM, but I am not able to make this work using blockram. Could someone help?
Instantiation:
I have tried a lot, and at this time, I have the following assertions for read/writing to the memory:
What must be changed for this to work?
Thanks.
Can someone point me out how I can read/write to the following blockram RAM model ?
I can read and write to external SRAM, but I am not able to make this work using blockram. Could someone help?
Code:
ENTITY vram8k IS
PORT
(
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
rdclock : IN STD_LOGIC ;
rden : IN STD_LOGIC := '1';
wraddress : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
wrclock : IN STD_LOGIC ;
wren : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END vram8k;
Instantiation:
Code:
vram8k_inst : work.vram8k PORT MAP (
data => v_data_sig,
rdaddress => v_address_r_sig(12 downto 0),
rdclock => Clk_Z80,
wraddress => v_address_w_sig(12 downto 0),
wrclock => Clk_Z80,
wren => vram_we_sig,
rden => vram_re_sig,
q => vram_q_sig
);
I have tried a lot, and at this time, I have the following assertions for read/writing to the memory:
Code:
v_address_w_sig <= A - x"2000" when (A >= x"2000" and MReq_n = '0');
v_address_r_sig <= A - x"2000" when (A >= x"2000" and MReq_n = '0');
vram_we_sig <= Wr_n;
vram_re_sig <= Rd_n;
v_data_sig <= DO_CPU when (Wr_n = '0' and MReq_n = '0');
DI_CPU <= vram_q_sig when (Rd_n = '0' and MReq_n = '0' and A >= x"2000");
What must be changed for this to work?
Thanks.