kelvin_sg
Advanced Member level 4
split using underscore
In Verilog one can split the bit-string with _.. "1111_0000_0001"..
for readability..
In VHDL what trick can I use?
In Verilog one can split the bit-string with _.. "1111_0000_0001"..
for readability..
In VHDL what trick can I use?