Wenf.Yeh
Junior Member level 3
Hi guyes
I have a design,When I synthesis it without DFT insertion, my design didn't has a hold time violation.
But when I synthesis design with the following script,it has worst hold time violation of -30ns in the timing group of sys clock.
### Test Insertion begin ###
set hdlin_enable_rtldrc_info true
set test_default_scan_style multiplexed_flip_flop
set test_default_period 100
set test_default_delay 0
set test_default_bidir_delay 0
set test_default_strobe 40
create_test_protocol -infer_clock -infer_async
compile -scan
set_scan_configuration -replace false
# Scan Insertion
insert_dft
### Test Insertion end ###
the drc check have been proseeded.
should I fix the hold time violation or just neglect it? or should I do some settings to disable the hold time checking for TE and TI signal?
I have a design,When I synthesis it without DFT insertion, my design didn't has a hold time violation.
But when I synthesis design with the following script,it has worst hold time violation of -30ns in the timing group of sys clock.
### Test Insertion begin ###
set hdlin_enable_rtldrc_info true
set test_default_scan_style multiplexed_flip_flop
set test_default_period 100
set test_default_delay 0
set test_default_bidir_delay 0
set test_default_strobe 40
create_test_protocol -infer_clock -infer_async
compile -scan
set_scan_configuration -replace false
# Scan Insertion
insert_dft
### Test Insertion end ###
the drc check have been proseeded.
should I fix the hold time violation or just neglect it? or should I do some settings to disable the hold time checking for TE and TI signal?