High current consumption from gates meant for up and down translation

[Plecto]

I'm using a SN74LV1T08DBVR as a 1.8V to 3.3V translator, but I just figured out that it draws huge amounts of current if one of it inputs is set somewhere between GND and VCC (as with other CMOS inputs). The datasheet clearly states that it can be used as a 1.8V to 3.3V translator, but the current draw becomes unacceptable for this application. I'm sort of bummed out as I've found these level translating gates to become very useful in my applications, but this current draw renders them useless. Does anyone else has any thoughts on this?

 

[KlausST]

Hi,

Huge ammount of currents

--> what does it mean? KiloAmperes?

if one of it inputs is set somewhere between GND and VCC

--> what signal input voltage? What is the IC's supply voltage?

current draw becomes unacceptable for this application

--> then please tell us what is "acceptable for your application"

Why don't you show a schematic?

How can we help?

It's quite typical for logic gates to draw higher Icc when the input voltage are in an invalid region....
Icc is lowest, when input levels are close to supply rails.

Klaus

 

[FvM]

The graph from TI "Low-Voltage-Logic-Families" product broschure suggests that LVT isn't well suited for this application, at least if you rely on low quiescent current.



If low static current consumption is an objective, you better go for dedicated translation IC with dual supply like SN74AUP1T34 or SN74AVC4T234.

 

[Plecto]

Thank you FvM. I was thinking the same, that I have to use a dedicated dual supply IC to get very low quiescent current.