high accuracy sample and hold

[rogger123]

i am using the above sample and hold circuit for a 16-bit ADC>
the switch is realised using both nmos(W=500n L=1.6u) and pmos(W=1u L=1.6u).
the input voltage range is 0-2v. the sampling freq is 200Hz.my sample pulse width is 100usec and hold period is 4.9msec.
when in hold mode the voltage at the output first starts increasing and then starts decreasing (in the order of 1-2mv). can any one suggest why this is happening.
i have also tried the basic circuit with a capacitor and a switch(nmos & pmos) the same problem occurs.
can any one suggest why this is happening. or suggest some different s&H architecture.
i need an accuracy of up to 30uV.

please help ! !

 

[guamak_menanak]

Actually,what technology did you use in your design?

Actually I'm not sure why the problem occured, but in my opinion...maybe the problem happens because of your op-amp is not capable to handle such input! Have you test your op-amp independently? What is your gain(Av) and f3dB for the op-amp?

I think if you give the op-amp spec, someone can help you better about your problem!

 

[rogger123]

I have tested the opamp individually and it works correctly..
i have tried a very basic circuit of a simple nmos-pmos switch and the same problem happens..
i am using 1.6uM technology....

 

[refdv]

there may be also efect of parasitic capasitance on the switch if you are using mos transister as your switching devise.