Hex to binary value comparison

[sara1983]

Hi,
I am doing a comparison between 2'h08 < 4'b1001 is false... how the conversion of bases happen...?? Can someone please explain ??

Thanks!
Satish

 

[ThisIsNotSam]

Hi,
I am doing a comparison between 2'h08 < 4'b1001 is false... how the conversion of bases happen...?? Can someone please explain ??

Thanks!
Satish

you need to read how verilog represents constants. it is not about conversion, it is about bits.

 

[dpaul]

@sara1983 ,
What you are doing is this : 8'b00001000 < 4'b1001

 

[FvM]

What you are doing is this : 8'b00001000 < 4'b1001

Not quite right. the size constant "2" in 2'h08 means two bits. According Verilog LRM IEEE 1800:

The first token, a size constant, shall specify the size of the integer literal constant in terms of its exact
number of bits. It shall be specified as a nonzero unsigned decimal number. For example, the size
specification for two hexadecimal digits is eight because one hexadecimal digit requires 4 bits.

The compiler should give a warning that the specified number value exceeds the bit length. The actual value would be 2'b00, the intended constant is 8'h08. The other question is, what happens if you compare integers of different bit length.

--- Updated Sep 20, 2021 ---

According to LRM

If the operands are of unequal bit lengths, the smaller operand shall be zero-extended to the size of the larger operand.

Respectively the actual relational expression is 8'b0000 < 8'b1001, value should be 1 (true). Presumed, the original post doesn't hide some important information, e.g. the numbers are signed rather than unsigned.

 

[dpaul]

Apologies....
I assumed 2'h was 2x hex, i.e. 8 bits!

 

[FvM]

Curiously, the comparison result would be 1 in both cases, there must be another hidden point. Need to see the complete code containing the comparison.

 

[sara1983]

Does that mean for example 1'ha would evaluate to 0 (4'b1010).... can someone please confirm...??

 

[FvM]

Example, if I write

state <= state + 1'd9;

I get a warning

Warning (10229): Verilog HDL Expression warning at data_convert.v(22): truncated literal to match 1 bits

The number is actually read as 1'd1.

 

[KlausST]

Does that mean for example 1'ha would evaluate to 0 (4'b1010).... can someone please confirm...??

If I understand post#8 correctly then

1´ha = 1 bit of 0x0a (0b00001010) --> 0b0 = 1´b0

Klaus