Help with interview question

[AdityaG]

Dear All

In a recent interview i was asked to design a logic for the following situation.

A pulse train is being fed at input side randomly at an average frequency of 20 Mbps. It is to be displayed correctly in same sequence as received, at the receiving end, at a frequency of 50 Mhz.

How would you do this?

Kindly help.

Thank you.

 

[shitansh]

Hi,

First at receiver side made two flop of pulse (coming from 20mbps freq domain) in 50Mhz clock domain to avoid metastability. (google for clock crossing domain)

Then simple LFSR is fine.

HTH
Shitansh Vaghela

 

[AdityaG]

Hi ..thanks for the prompt response.

However, can u please elaborate on your answer?

He gave me an example of a pulse sequence..lets say "..101111001...." so on...goal is to get this exact same sequence pulsed out at 50 Mhz. No data bit should repeat itself, obviously.

Data is not sent at fixed time intervals...but at an average frequency of 20 Mbps.

So how does a simple LFSR fit in the picture? Data input is not in our hands..it is fed from an external source.

A point to note: he was trying to give me some hints by specifying some "data valid" and "data invalid" flags...how do they come into picture in this scenario or with an LFSR?

Please help.

Hi,

First at receiver side made two flop of pulse (coming from 20mbps freq domain) in 50Mhz clock domain to avoid metastability. (google for clock crossing domain)

Then simple LFSR is fine.

HTH
Shitansh Vaghela

 

[vipinlal]

I dont think a simple LFSR will work.
You need a FIFO buffer for implementing this. The input data is read into the buffer.Once the data in buffer reaches beyond a threshold level(may be half of buffer size) you can start taking data from the buffer at constant 50 MHz.
The problem here is that you have to carefully design the buffer size.Otherwise data delay will be more.Also your date read rate is 2.5 times than that of your average write rate.This may creat a problem after some time,because there may not be any data available in the buffer after some time.

A simple solution will not work.You have to make suitable assumptions for the design.

--vipin
https://vhdlguru.blogspot.com/

 

[user_asic]

Whats the length of the sequence of bits? Does it vary?

 

[AdityaG]

No particular length...
bits are continuously appearing at input.

Maybe certain assumptions will have to be made, as the problem seems ambiguous..

Whats the length of the sequence of bits? Does it vary?

 

[user_asic]

Since the question was a little ambiguous, use that your advantage! A serial-parallel converter assuming a modest 8 bit sequence. You can have the 8 lines from the serial-parallel converter's output going to FFs, then have an enable signal going to a MUX recirculation circuit, which only captures data when the enable signal is high, otherwise it just recirculates the output of the 50MHz clock domain.

Instead you have also have a single flop and capture every bit on the enable signal. Although the enable signal might be slightly tricky in this case.

https://asic-interview.blogspot.com/2010/01/clock-domain-crossing-timing-q.html