Cesar0182
Member level 5
I tell you that I am new to this forum, I have limited knowledge of vhdl, but I am a novice in verilog. A couple of days ago I'm trying to translate a module from a verilog project to vhdl, but this makes use of other modules, I have managed to translate this, but I have problems translating the following lines of a module
Can someone please help me with this, thanks in advance.
Code:
`define WBUSRANGE 32*idx+31:32*idx // Incrementing indexes within generate below
generate
genvar idx;
for (idx=0; idx<=25; idx = idx+1)
assign o_wbus_count[10*idx+9:10*idx] = wbus_count[idx];
wire wen = i_wbus_enable[idx] & i_wbus_wen & upper_adrs_match &
& (i_wbus_addr[20:16] == i_wbus_fws[5*idx+4:5*idx]);
wire almost_full_d = i_wbus_enable[idx] & ( ff_write_count >
Almost_Full_Depth );
dreg_clr #(1) dc_amf( .c( i_aur_clk ), .ar( i_rst ), .e( 1'b1 ), .d(
almost_full_d ), .q( almost_full[idx] ) );
assign o_wbus_waddr[`WBUSRANGE] = {13'h0, ff_dout[50:32]};
assign o_wbus_wdata[`WBUSRANGE] = ff_dout[31:0];
end
endgenerate
Can someone please help me with this, thanks in advance.