help required in designing of phase detector and VCO for PLL

[hemal]

linear range of phase detector

hi,

i have a project of designing a high speed PLL. 0.18um technology with 1.8V as supply

i have designed individual components of the pll.

CMOS current sterved VCO is giving 333khz at 0.5V input bias and 1.2GHz at 1.4V input bias. Due to this nonlinear behavior i am not getting stable output at the input of VCO that is the filter output has ripples and if the ripples is are upto 5mv then also the frequency changes very much.

if i want to remove the ripples then very large capacitors are required in the low pass filter.

so what is the solution to reduce the frequency range of the VCO so that the output of a low pass filter can be stable?

thanks,

hemal

 

[LvW]

phase detector spice behavioral model

hi,
CMOS current sterved VCO is giving 333khz at 0.5V input bias and 1.2GHz at 1.4V input bias. Due to this nonlinear behavior i am not getting stable output at the input of VCO that is the filter output has ripples and if the ripples is are upto 5mv then also the frequency changes very much.
if i want to remove the ripples then very large capacitors are required in the low pass filter.

I don´t think that the observed ripple is caused by some nonlinear VCO behaviour.
Instead you should beware of the fact that the output of the phase/frequency detector contains - in addition to the desired control signal - always some higher frequency components. These can be attenuated somewhat by a carefully designed lowpass filter.
First question: What kind of detector do you use ?
2nd question: What kind of loop filter do you use ?
(activ, passiv, order ?, with zeros ?)

 

[hemal]

designing a vco for pll

hi,

i am using the phase detector made up with two D flipflop and one and gate. the loop filter is of second order. i have also tried third order loop filter upto capacitor range of 2 nf. the cutoff frequency of the loop filter is 7.98KHz.

can u tell me how to get the Kvco for VCO for the following frequency range.

Vbias = 0.5V fvco = 330KHz

Vbias = 1.4V fvco = 1.2GHz

i know it turns a vary large in number. Is it realistic?.

thanks.

 

[Teddy]

vco bias ripple filter

Well I woul dsay that VCO like this would work but you would like to have a nice linear range of about 20% arround center frequency.

If your input reference is 333kHz then run VCO at 1.2G and divide it down.

The way you have it you would have really hard time to make working filter. Your observation of a large cap is correct - if 333kHz then you need to set filter to 33K - good luck with that.

 

[hemal]

phase detector

hi,

can u suggest me the way to get the vco frequency range of 20% of its center frequency? i am using current sterved VCO given in the book by baker.

thanks

 

[LvW]

design a phase detector

hi,
i am using the phase detector made up with two D flipflop and one and gate. the loop filter is of second order. i have also tried third order loop filter upto capacitor range of 2 nf. the cutoff frequency of the loop filter is 7.98KHz.

Question: I doubt that your loop can be stable; are your results derived from measurements or simulations ?
Background of my doubts: With a second order loop filter your PLL system is of third order - and most probably unstable.
Normally, a first order filter with a properly designed zero is used or , aleternatively, a PI controller (second order with a zero is possible, but hard to design) .

 

[hemal]

phase frequency detector spice

hi,

i have tried 1st and 2nd order loop filter. But i am not getting the stable output at the loop fiter. There are variation of about 7-8mv which changes my stable frequency. what could be the reason for that? all the components individually working fine. but when i am integrating it it does not remain stable after some time. i am using the spice simultion to verify design.

thanks.

 

[LvW]

nonlinear vco pspice

hi,
i have tried 1st and 2nd order loop filter. But i am not getting the stable output at the loop fiter. There are variation of about 7-8mv which changes my stable frequency. what could be the reason for that? all the components individually working fine. but when i am integrating it it does not remain stable after some time. i am using the spice simultion to verify design.
thanks.

As I have mentioned in my reply dated august 14th, 17:12, it is quite normal that the output of the loop filter - even if the loop is stable - exhibits some ripple as it never can filter out the unwanted components completely . What is the FREQUENCY of this ripple ?
But remember, a 2nd order loop filter without a zero creates instabilty !

Added later: But remember, a 2nd order loop filter without a zero creates instabilty , unless the second pole is far outside the loop bandwidth (that means it is a non-dominating pole)

 

[alvays]

designing of phase detector

hemal
you can upload your loop parameter and pfd/charge pump type. then we can check it more specifically.
what's your center frequency.
---alvays

 

[hemal]

nf phase detector

hi,
thanks for your response. I have designed the PLL and simulated it. Now i want to measure the phase noise.

Here are my parameter values:

Kvco = 287 MHz /V
Kcp = 2*1 e-6/(2*pi)
Wn = 6 * 1E6
Rp = 20K
C1 = 5pF
C2 = 0.1pF

can u tell me how to measure the phase noise for above parameters?
or is there anything missing?

thanks

hemal