hemal
Junior Member level 2
linear range of phase detector
hi,
i have a project of designing a high speed PLL. 0.18um technology with 1.8V as supply
i have designed individual components of the pll.
CMOS current sterved VCO is giving 333khz at 0.5V input bias and 1.2GHz at 1.4V input bias. Due to this nonlinear behavior i am not getting stable output at the input of VCO that is the filter output has ripples and if the ripples is are upto 5mv then also the frequency changes very much.
if i want to remove the ripples then very large capacitors are required in the low pass filter.
so what is the solution to reduce the frequency range of the VCO so that the output of a low pass filter can be stable?
thanks,
hemal
hi,
i have a project of designing a high speed PLL. 0.18um technology with 1.8V as supply
i have designed individual components of the pll.
CMOS current sterved VCO is giving 333khz at 0.5V input bias and 1.2GHz at 1.4V input bias. Due to this nonlinear behavior i am not getting stable output at the input of VCO that is the filter output has ripples and if the ripples is are upto 5mv then also the frequency changes very much.
if i want to remove the ripples then very large capacitors are required in the low pass filter.
so what is the solution to reduce the frequency range of the VCO so that the output of a low pass filter can be stable?
thanks,
hemal