LatticeSemiconductor
Member level 2
Hi all,
I am trying to use true random values to feed my testbench for functional simulation. I am using the random package from OSVVM but the sequence is pseudo random. Is it possible to use system time to generate the seed in VHDL?
I want to use the system time not simulation time, so i have different values each time i run the simulation. I could not find any VHDL example for a true random generator. Is it a bad idea to configure simulation randomly? I know i should rather aim for coverage, i am still a beginner on that topic.
- - - Updated - - -
I just found the $gettime command. Trying to use this in my simulation macro file, then pass it throu a generic to my testbench. It is Aldec spezific though, and i don't know the data type it returns.
I am trying to use true random values to feed my testbench for functional simulation. I am using the random package from OSVVM but the sequence is pseudo random. Is it possible to use system time to generate the seed in VHDL?
I want to use the system time not simulation time, so i have different values each time i run the simulation. I could not find any VHDL example for a true random generator. Is it a bad idea to configure simulation randomly? I know i should rather aim for coverage, i am still a beginner on that topic.
- - - Updated - - -
I just found the $gettime command. Trying to use this in my simulation macro file, then pass it throu a generic to my testbench. It is Aldec spezific though, and i don't know the data type it returns.